1. Field of the Invention
This disclosure relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a reliable high performance capacitor using an isotropic etching process.
2. Description of Related Art
Memory devices such as DRAM devices require a high performance cell capacitor with sufficient capacitance in order to increase both its refresh period and its tolerance to alpha particles. However, to implement this high performance cell capacitor, it is necessary to either increase the area between an upper electrode (plate electrode) and a lower electrode (storage node electrode) that overlaps, or reduce the thickness of a dielectric film interposed between the upper and lower electrodes. In addition, this second option requires that the dielectric film between the electrodes be made of a material having a high dielectric constant.
Recently, a method of increasing the height of the storage node electrode has been widely used in order to implement this desired high performance capacitor. In this method, a surface area of the storage node electrode is increased, whereby the capacitance of the capacitor is increased.
This method of forming the cell capacitor is taught in U.S. Pat. No. 6,459,112 to Tsuboi et al. entitled “Semiconductor device and process for fabricating the same.” FIGS. 1A through 1C are cross-sectional views illustrating a method of forming a capacitor as disclosed in U.S. Pat. No. 6,459,112.
Referring to FIG. 1A, an insulating layer 20 is formed on a semiconductor substrate 10. The insulating layer 20 is patterned, using a photolithography technique and an etching technique, to form node contact holes which expose predetermined regions of the semiconductor substrate 10. The node contact holes are filled with a conductive material to form contact plugs 25.
Referring to FIG. 1B, an etch stopping layer 30 and a sacrificial oxide layer 40 are sequentially formed over the surface of the semiconductor substrate having the contact plugs 25. The sacrificial oxide layer 40 is patterned to form capacitor holes exposing predetermined regions of the etch stopping layer 30. The exposed portion of the etch stopping layer 30 is then dry-etched to form final capacitor holes which expose the top surfaces of the contact plugs 25 and neighboring portions of the insulating layer 20 around the top surface of the contact plugs 25. Here, the etch stopping layer 30 is over-etched, so that the exposed portions of the contact plugs 25 and the neighboring portions of the insulating layer 20 are etched by a predetermined depth.
An oxide layer cleaning process is performed using a hydrofluoric acid as a cleaning solution to isotropically etch a portion of the insulating layer 20 under the etch stopping layer 30 and the sacrificial oxide layer 40, thereby forming cleaned capacitor holes 45.
Referring to FIG. 1C, a polysilicon layer is formed over the entire surface of the semiconductor substrate having the cleaned capacitor holes 45. A portion of the polysilicon layer above the sacrificial oxide layer 40 is selectively removed, and then the sacrificial oxide layer 40 is selectively removed, thereby forming lower electrodes 50 of the capacitor.
According to U.S. Pat. No. 6,459,112, polymers and native oxide films in the final capacitor holes are removed by a single step of cleaning process before forming the polysilicon layer in the cleaned capacitor holes 45. Therefore, a lengthy cleaning process is required in order to maximize the diameters of the cleaned capacitor holes 45. Such a long cleaning process time may lead to the formation of through holes in the portion of the insulating layer 20 between the final capacitor holes. This, in turn, causes a problem where the lower electrodes are electrically connected to each other.
However, if the cleaning process is performed in a shorter time interval to prevent the through hole from being formed, it is difficult to maximize the diameters of the final capacitor holes. Consequently, it is difficult to optimize the cleaning process.